 
\subsection{RISC-V Soft CPU}

The firmware in the CryptoCore uses a soft CPU with a 32-bit implementation of the RISC-V instruction set called "VexRiscv". This implementation won the RISC-V foundation's soft CPU competition in 2018, and comes with the following benefits:
\begin{itemize}
 \item Written in the Scala programming language, which means you can extend it through plugins.
 \item Licensed under MIT, which allows you to use it in commercial environments.
\end{itemize}

\subsubsection{Memory Map}
 
\begin{tabular}{|r|r|l|}
\hline
Address & Size & Comment \\
\hline
 0x00000000 & 128kB & ROM \\
 0x80000000 & 128kB & RAM \\
 0x84000000 & 4kB & Secured RAM \\
 0xF1030000 & 64kB & GPIO pins and alternate functions (AF) switch \\
 0xF1040000 & 64kB & SPI master\\
 0xF1070000 & 64kB & UART \\
 0xF10A0000 & 64kB & I2C master \\
 0xF4000000 & 64kB & Secure element \\
 0xF4010000 & 64kB & System timer \\
 0xF4020000 & 64kB & QSPI master for QSPI flash \\
 0xF4030000 & 4kB & RAM for the converter \\
 0xF4040000 & 64kB & Converter (trits/trytes $\Leftrightarrow$ bits/bytes) \\
 0xF4050000 & 64kB & PiDiver (hashing) \\
\hline

\end{tabular}
 
\paragraph{ROM, RAM, Secured RAM} 
The ICCFPGA module supports 128 kB ROM, 128 kB RAM, as well as an additional 4 kB of RAM, which only is accessible in privileged modes. It is used as key-store for the AES encryption key (for decrypting communicatios received from the Secure Element) and API key. Also it is used in Machine-mode as protected memory for stack.

\paragraph{Secure Element}
The secure element is attached to the I2C interface, which is accessible only in Supervisor mode. This interface also is used for booting alternative bitstreams from flash memory.

\paragraph{PiDiver}
The PiDiver component accelerates hashing such as Curl-P81, Keccak384 (SHA3) and Troika. It also does Proof-of-Work. All hashing-algorithms need a single clock-cycle per hashing-round.

\paragraph{Converter}
The converter converts binary data to/from ternary.

\paragraph{GPIO Pins and the Alternate Functions (AF) Switch}
There are 19 GPIO pins, which can be used as digital inputs or outputs. Pins 0 to 8 can changed to use as SPI, I2C, and UART. The base component is an AXI GPIO, for which documentation can be found here: \url{https://www.xilinx.com/support/documentation/ip_documentation/axi_gpio/v2_0/pg144-axi-gpio.pdf}.

The GPIO periphery is used for reading/writing the GPIO pins and for changing their function.

The first GPIO channel is used for the actual GPIO pins, where each one can be configured to be an input or an output.

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|}
\hline
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24 & 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16 \\
\hline
 LCK &  x &  x &  x &  x &  x &  x &  x &  x &  x &  x &  LEDL &  LEDU &  IO18 &  IO17 &  IO16 \\
\hline
\multicolumn{16}{c}{} \\
\hline
15 & 14 & 13 & 12 & 11 & 10 &  9 &  8 &  7 &  6 &  5 &  4 &  3 &  2 &  1 &  0 \\
\hline
 IO15 &  IO14 &  IO13 &  IO12 &  IO11 &  IO10 &  IO9 &  IO8 &  IO7 &  IO6 &  IO5 &  IO4 &  IO3 &  IO2 &  IO1 &  IO0 \\
 \hline
\end{tabular}

GPIO pins 19 and 20 are wired to two LEDs on the ICCFPGA module. Pin IO19 is connected to ``LED User'', and pin IO20 is connected to ``LED Lock''. Pin 31 always reads the LOCK bit in the JTAG peripheral, which is routed to the GPIO pins. 

Alternate function for GPIO pins:
\begin{itemize}
 \item IO0 (MOSI), IO1 (MISO), IO2 (SCK), IO3 (SS0), IO4 (SS1): SPI master with two slave-select lines
 \item IO5 (SCL), IO6 (SDA): I2C master
 \item IO7 (RXD) , IO8 (TXD): UART
\end{itemize}

Alternate functions can be selected by writing a '1' to the corresponding bit location of the second GPIO channel of the AXI GPIO.

\paragraph{SPI Master}
The SPI master supports two slaves, and is connected to the AF switch (pins 0 to 4). AXI documentation: \url{https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf}

\paragraph{QSPI Master}
The QSPI master is connected to the 16 MB flash storage on the ICCFPGA module, and is used for automatically configuring it at boot. and is accessible from the soft CPU, which allows you to update the bitstream. AXI-Documentation: \url{https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf}

\paragraph{UART}
The UART is used for input and output of data to/from the ICCFPGA module. If no UART is needed, the UART pins can be used as GPIO pins by disabling the function in the AF switch (GPIO pins 7 to 8). AXI documentation: \url{https://www.xilinx.com/support/documentation/ip_documentation/axi_uartlite/v2_0/pg142-axi-uartlite.pdf}

\paragraph{Converter RAM}
The converter RAM is used by the converter when converting data to/from binary and ternary.

\paragraph{System Timer}
The system timer generates timer interrupts with a frequency of 1 kHz for time measurements or delays in software.

\paragraph{I2C Master}
The I2C master can be used to attach I2C peripherals to the ICCFPGA module. It also is connected to the AF switch (pins 5 and 6).

